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2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 1 2, 4 meg x 72 buffered dram dimms obsolete dram module MT9LD272(x), mt18ld472(f)(x) for the latest data sheet, please refer to the micron web site: www.micronsemi.com/datasheets/datasheet.html pin assignment (front view) pin symbol pin symbol pin symbol pin symbol 1v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 oe2# 86 dq36 128 r f u 3 dq1 45 ras2# 87 dq37 129 n c 4 dq2 46 cas4# 88 dq38 130 n c 5 dq3 47 rfu 89 dq39 131 r f u 6v dd 48 we2# 90 v dd 132 pde# 7 dq4 49 v dd 91 dq40 133 v dd 8 dq5 50 n c 92 dq41 134 n c 9 dq6 51 n c 93 dq42 135 n c 10 dq7 52 dq18 94 dq43 136 dq54 11 dq8 53 dq19 95 dq44 137 dq55 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq20 97 dq45 139 dq56 14 dq10 56 dq21 98 dq46 140 dq57 15 dq11 57 dq22 99 dq47 141 dq58 16 dq12 58 dq23 100 dq48 142 dq59 17 dq13 59 v dd 101 dq49 143 v dd 18 v dd 60 dq24 102 v dd 144 dq60 19 dq14 61 rfu 103 dq50 145 r f u 20 dq15 62 rfu 104 dq51 146 r f u 21 dq16 63 rfu 105 dq52 147 r f u 22 dq17 64 rfu 106 dq53 148 r f u 23 v ss 65 dq25 107 v ss 149 dq61 24 n c 66 dq26 108 n c 150 dq62 25 n c 67 dq27 109 n c 151 dq63 26 v dd 68 v ss 110 v dd 152 v ss 27 we0# 69 dq28 111 r f u 153 dq64 28 cas0# 70 dq29 112 n c 154 dq65 29 rfu 71 dq30 113 r f u 155 dq66 30 ras0# 72 dq31 114 n c 156 dq67 31 oe0# 73 v dd 115 r f u 157 v dd 32 v ss 74 dq32 116 v ss 158 dq68 33 a0 75 dq33 117 a1 159 dq69 34 a2 76 dq34 118 a3 160 dq70 35 a4 77 dq35 119 a5 161 dq71 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 pd1 121 a9 163 pd2 38 a10 80 pd3 122 a11 164 pd4 39 nc (a12) 81 pd5 123 nc (a13) 165 pd6 40 v dd 82 pd7 124 v dd 166 pd8 41 rfu 83 id0 125 rfu 167 id1 42 r f u 84 v dd 126 b0 168 v dd features ? jedec-standard ecc pinout in a 168-pin, dual in- line memory module (dimm) ? 16mb (2 meg x 72) and 32mb (4 meg x 72) ? high-performance cmos silicon-gate process ? single +3.3v 0.3v power supply ? all inputs, outputs and clocks are ttl-compatible ? refresh modes: ras#-only, cas#-before- ras# (cbr) and hidden ? all inputs are buffered except ras# ? 2,048 cycles (11 row, 11 column addresses) or 4,096 cycles (12 row, 10 column addresses) ? fast-page-mode (fpm) or extended data-out (edo) page mode access cycles options marking ? package 168-pin dimm (gold) g ? timing 50ns access -5* 60ns access -6 ? access cycles fast page mode none edo page mode x ? refresh 2,048 cycles across 32ms none 4,096 cycles across 64ms (32mb only) f * edo version only 168-pin dimm note: pin symbols in parentheses are not used on these modules but may be used for other modules in this product family. they are for reference only. key timing parameters edo operating mode speed t rc t rac t pc t aa t cac t cas -5 84ns 50ns 20ns 30ns 18ns 8ns -6 104ns 60ns 25ns 35ns 20ns 10ns fpm operating mode speed t rc t rac t pc t aa t cac t rp -6 110ns 60ns 35ns 35ns 20ns 40ns
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 2 2, 4 meg x 72 buffered dram dimms obsolete part numbers edo operating mode part number configuration refresh MT9LD272g-x x 2 meg x 72 ecc 2k refresh mt18ld472g-x x 4 meg x 72 ecc 2k refresh mt18ld472fg-x x 4 meg x 72 ecc 4k refresh x = speed fpm operating mode part number configuration refresh MT9LD272g-x 2 meg x 72 ecc 2k refresh mt18ld472g-x 4 meg x 72 ecc 2k refresh mt18ld472fg-x 4 meg x 72 ecc 4k refresh x = speed general description the MT9LD272(x) and mt18ld472(f)(x) are ran- domly accessed 16mb and 32mb memories organized in a x72 configuration. they are specially processed to operate from 3v to 3.6v for low-voltage memory systems. during read or write cycles, each bit is uniquely addressed through the address bits. two copies of address 0 (a0 and b0) are defined to allow maximum performance for four-byte applications which inter- leave between two four-byte banks. a0 is common to the drams used for dq0-dq35, while b0 is common to the drams used for dq36-dq71. ras# is used to latch the first 11/12 bits and cas# the latter 10/11 bits. read and write cycles are selected with the we# input. a logic high on we# dictates read mode, while a logic low on we# dictates write mode. during a write cycle, data-in (d) is latched by the falling edge of we# or cas#, whichever occurs last. an early write occurs when we# is taken low prior to cas# falling. a late write or read-modify-write oc- curs when we# falls after cas# was taken low. during early write cycles, the data-outputs (q) will remain high-z regardless of the state of oe#. during late write or read-modify-write cycles, oe# must be taken high to disable the data-outputs prior to applying input data. if a late write or read- modify-write is attempted while keeping oe# low, no write will occur, and the data-outputs will drive read data from the accessed location. fast page mode fast-page-mode operations allow faster data operations (read or write) within a row-address- defined page boundary. the fast-page-mode cycle is always initiated with a row address strobed in by ras#, followed by a column address strobed in by cas#. additional columns may be accessed by provid- ing valid column addresses, strobing cas# and hold- ing ras# low, thus executing faster memory cycles. returning ras# high terminates the fast-page- mode operation. edo page mode edo page mode, designated by the x version, is an accelerated fast-page-mode cycle. the pri- mary advantage of edo is the availability of data-out even after cas# goes back high. edo provides for cas# precharge time ( t cp) to occur without the out- put data going invalid. this elimination of cas# output control provides for pipelined reads. fast-page-mode modules have traditionally turned the output buffers off (high-z) with the rising edge of cas#. edo-page-mode drams operate like fast-page-mode drams, except data will remain valid or become valid after cas# goes high during reads, provided ras# and oe# are held low. if oe# is pulsed while ras# and cas# are low, data will toggle from valid data to high-z and back to the same valid data. if oe# is toggled or pulsed after cas# goes high while ras# remains low, data will transition to and remain high-z. during an application, if the dq outputs are wire ord, oe# must be used to disable idle banks of drams. alternatively, pulsing we# to the idle banks during cas# high time will also high-z the outputs. inde- pendent of oe# control, the outputs will disable after t off, which is referenced from the rising edge of ras# or cas#, whichever occurs last. (refer to the 4 meg x 4 [mt4lc4m4e8] dram data sheet for additional in- formation on edo functionality.) refresh returning ras# and cas# high terminates a memory cycle and decreases chip current to a reduced standby level. also, the chip is preconditioned for the next cycle during the ras# high time. correct memory cell data is preserved by maintaining power and ex- ecuting any ras# cycle (read, write) or ras# re- fresh cycle (ras#-only, cbr or hidden) so that all combinations of ras# addresses are executed at least every t ref, regardless of sequence. the cbr refresh cycle will invoke the internal refresh counter for auto- matic ras# addressing.
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 3 2, 4 meg x 72 buffered dram dimms obsolete functional block diagram MT9LD272(x) (16mb) d d d a10-a1 d d d oe0# we0# cas0# ras0# d d a0 dq0-dq7 u9 a1ea10 dq0-dq7 dq0-dq7 u4 u3 a1ea10 dq0-dq7 dq0-dq7 u2 u7 a1ea10 a1ea10 dq0-dq7 u8 a1ea10 a10 d a1 a1ea10 dq0-dq7 u1 a1ea10 a0 we# oe# ras# cas# a0 we# oe# ras# cas# a0 we# oe# ras# cas# a0 we# oe# ras# cas# a0 we# oe# ras# cas# a0 we# oe# ras# cas# a0 we# oe# ras# cas# dq0-dq7 u5 a1ea10 dq0-dq7 dq64-dq71 dq16-dq23 dq24-dq31 dq8-dq15 dq48-dq55 dq56-dq63 dq0-dq7 dq32-dq39 dq40-dq47 u6 a1ea10 u1-u9 = mt4lc2m8b1 fast page mode u1-u9 = mt4lc2m8e7 edo page mode pde# pd1-pd8 e# presence detect generator oe2# we2# cas4# ras2# b0 10 10 10 10 10 10 10 10 10 10 v dd v ss u1-u9, buffers u1-u9, buffers a0 we# oe# ras# cas# a0 we# oe# ras# cas# note: 1. all inputs, with the exception of ras#, are redriven. 2. d = line buffers.
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 4 2, 4 meg x 72 buffered dram dimms obsolete note: 1. all inputs with the exception of ras# are redriven. 2. d = line buffers. functional block diagram mt18ld472(f)(x) (32mb) dq0-dq3 dq4-dq7 dq8-dq11 dq12-dq15 dq16-dq19 dq20-dq23 dq24-dq27 dq28-dq31 dq32-dq35 dq36-dq39 dq40-dq43 dq44-dq47 dq48-dq51 dq52-dq55 dq56-dq59 dq60-dq63 dq64-dq67 dq68-dq71 mt18ld472fg (4k refresh) u1-u18 = mt4lc4m4a1 fast page mode mt18ld472fg x (4k refresh) u1-u18 = mt4lc4m4e9 edo page mode d d d d oe0# d d we0# cas0# oe2# we2# cas4# a11-a1 ras0# ras2# a1ea11 a0 we# oe# ras# cas# a1ea11 a0 we# oe# ras# cas# a1ea11 a0 we# oe# ras# cas# a1ea11 a0 we# oe# ras# cas# a1ea11 a0 we# oe# ras# cas# a1ea11 a0 we# oe# ras# cas# a1ea11 a0 we# oe# ras# cas# a1ea11 a0 we# oe# ras# cas# d a0 d b0 a11 d a1 pde# pd1-pd8 e# presence- detect generator mt18ld472g (2k refresh) u1-u18 = mt4lc4m4b1 fast page mode mt18ld472g x (2k refresh) u1-u18 = mt4lc4m4e8 edo page mode v dd v ss u1-u18, buffers u1-u18, buffers a1ea11 a0 we# oe# ras# cas# a1ea11 a0 we# oe# ras# cas# a1ea11 a0 we# oe# ras# cas# a1ea11 a0 we# oe# ras# cas# a1ea11 a0 we# oe# ras# cas# a1ea11 a0 we# oe# ras# cas# a1ea11 a0 we# oe# ras# cas# a1ea11 a0 we# oe# ras# cas# a1ea11 a0 we# oe# ras# cas# a1ea11 a0 we# oe# ras# cas# dq0-dq3 u2 dq0-dq3 u3 dq0-dq3 u4 u5 dq0-dq3 u6 dq0-dq3 u7 dq0-dq3 dq0-dq3 u8 dq0-dq3 u9 u16 u17 u15 u18 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 u10 u11 u13 u14 u12 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 dq0-dq3 u1
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 5 2, 4 meg x 72 buffered dram dimms obsolete pin descriptions pin numbers symbol type description 30, 45 ras0#, ras2# input row-address strobe: ras# is used to clock-in the row- address bits. two ras# inputs allow for one x72 bank or two x36 banks. 28, 46 cas0#, cas4# buffered column-address strobe: cas# is used to clock-in the input column-address bits, enable the dram output buffers and strobe the data inputs on write cycles. 27, 48 we0#, we2# buffered write enable: we# is the read/write control for the input dq pins. we0# controls dq0-dq35. we2# controls dq36-dq71. if we# is low prior to cas# going low, the access is an early write cycle. if we# is high while cas# is low, the access is a read cycle, provided oe# is also low. if we# goes low after cas# goes low, then the cycle is a late write cycle. a late write cycle is generally used in conjunction with a read cycle to form a read-modify-write cycle. 31, 44 oe0#, oe2# buffered output enable: oe# is the input/output control for the input dq pins. oe0# controls dq0-dq35. oe2# controls dq36-dq71. these signals may be driven, allowing late write cycles. 33-38, 117-122, 126 a0-a11, b0 buffered address inputs: these inputs are multiplexed and input clocked by ras# and cas#. a0 is common to the drams used for dq0-dq35 while b0 is common to the drams used for dq36-dq71 2-5, 7-11, 13-17, 19-22, dq0-dq71 input/ data i/o: for write cycles, dq0-dq71 act as inputs to 52-53, 55-58, 60, 65-67, output the addressed dram location. for read access cycles, 69-72, 74-77, 86-89, dq0-dq71 act as outputs for the addressed dram 91-95, 97-101, 103-106, location. 136-137, 139-142, 144, 149-151, 153-156, 158-161 79-82, 163-166 pd1-pd8 buffered presence-detect: these pins are read by the host system output and tell the system the dimms personality. they will be either no connect (1), or they will be driven to v ol (0). 29, 41-42, 47, 61-64, 111, rfu C reserved for future use: these pins should be left 113, 115, 125, 128, 131, unconnected. 145-148 6, 18, 26, 40, 49, 59, 73, v dd supply power supp ly: +3.3v 0.3v. 84, 90, 102, 110, 124, 133, 143, 157, 168 1, 12, 23, 32, 43, 54, v ss supply ground. 68, 78, 85, 96, 107, 116, 127, 138, 152, 162 83, 167 id0, id1 output id bits: id0 = dimm type. id1 = refresh mode. these pins will be either left floating (nc) or they will be grounded (v ss ). 132 pde# input presence-detect enable: pde# is the read control for the buffered presence-detect pins.
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 6 2, 4 meg x 72 buffered dram dimms obsolete note: v ss = ground; v ol = 0; nc = 1. * this addressing includes a redundant address to allow mixing of 12/10 and 11/11 drams with the same presence-detect setting. presence-detect truth table characteristics presence-detect pin (pdx) module module row/column id0 id1 density configuration addresses 12345678 0mb no module installed x 1111 8mb 1 meg x 64/72 10/9 1100 8mb 1 meg x 64/72 10/10 0010 16mb 2 meg x 64/72 10/10 1010 ? 16mb 2 meg x 64/72 11/10 1001 32mb 4 meg x 64/72 11/10 0101 ? 32mb 4 meg x 64/72 12*/11* 1101 64mb 8 meg x 64/72 12*/11* 0011 page mode fast page mode 0 edo page mode 1 access timing 70ns 0 1 60ns 1 1 50ns 0 0 refresh control standard vss data width x64, no parity vss 1 x72, ecc vss 0
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 7 2, 4 meg x 72 buffered dram dimms obsolete dc electrical characteristics and operating conditions (notes: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v dd 3 3.6 v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v 36 input low voltage: logic 0; all inputs v il -0.5 0.8 v 36 input leakage current: cas0#, cas4#, any input 0v v in v dd + 0.3v a0-a11, b0, pde#, i i 1 -2 2 a (all other pins not under test = 0v) we0#, we2#, oe0#, oe2# ras0#-ras3# i i 2 -18 18 a output leakage current: dq0-dq71, i oz -5 5 a dq is disabled; 0v v out v dd + 0.3v pd1-pd8 output levels: v oh 2.4 C v output high voltage (i out = -2ma) output low voltage (i out = 2ma) v ol C 0.4 v absolute maximum ratings* voltage on v dd pin relative to v ss ........ -1v to +4.6v voltage on inputs or i/o pins relative to v ss ..................................... -1v to +4.6v operating temperature, t a (ambient) .. 0c to +70c storage temperature (plastic) ........... -55c to +125c power dissipation ................................................... 9w *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to abso- lute maximum rating conditions for extended periods may affect reliability.
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 8 2, 4 meg x 72 buffered dram dimms obsolete parameter/condition symbol size -5* -6 units notes standby current: ttl i cc 1 16mb 72 72 ma (ras# = cas# = v ih ) 32mb 90 90 standby current: cmos i cc 2 16mb 9 9 ma (ras# = cas# = v dd - 0.2v) 32mb 9 9 operating current: random read/write i cc 3 16mb 990 900 ma 3, 29 average power supply current 32mb 1,980 1,800 (ras#, cas#, address cycling: t rc = t rc [min]) operating current: fast page mode i cc 4 16mb C 720 ma 3, 29 average power supply current 32mb C 1,440 (ras# = v il , cas#, address cycling: t pc = t pc [min]) operating current: edo page mode (x version only) i cc 5 16mb 990 900 ma 3, 29 average power supply current (x only) 32mb 1,980 1,800 (ras# = v il , cas#, address cycling: t pc = t pc [min]) refresh current: ras#-only i cc 6 16mb 990 900 ma 3, 29 average power supply current 32mb 1,980 1,800 (ras# cycling, cas# = v ih : t rc = t rc [min]) refresh current: cbr i cc 7 16mb 990 900 ma 3, 4 average power supply current 32mb 1,980 1,800 (ras#, cas#, address cycling: t rc = t rc [min]) 2,048-cycle refresh i cc operating conditions and maximum limits (notes: 1, 5, 6) (v dd = +3.3v 0.3v) max * edo version only 4,096-cycle refresh i cc operating conditions and maximum limits (notes: 1, 5, 6) (v dd = +3.3v 0.3v) parameter/condition symbol size -5* -6 units notes standby current: ttl i cc 1 32mb 90 90 ma (ras# = cas# = v ih ) standby current: cmos i cc 2 32mb 9 9 ma (ras# = cas# = v dd - 0.2v) operating current: random read/write average power supply current i cc 3 32mb 1,620 1,440 ma 3, 29 (ras#, cas#, address cycling: t rc = t rc [min]) operating current: fast page mode average power supply current i cc 4 32mb C 1,260 ma 3, 29 (ras# = v il , cas#, address cycling: t pc = t pc [min]) operating current: edo page mode (x version only) i cc 5 average power supply current (x only) 32mb 1,800 1,620 ma 3, 29 (ras# = v il , cas#, address cycling: t pc = t pc [min]) refresh current: ras#-only average power supply current i cc 6 32mb 1,620 1,440 ma 3, 29 (ras# cycling, cas# = v ih : t rc = t rc [min]) refresh current: cbr average power supply current i cc 7 32mb 1,620 1,440 ma 3, 4 (ras#, cas#, address cycling: t rc = t rc [min]) max
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 9 2, 4 meg x 72 buffered dram dimms obsolete fast page mode ac electrical characteristics (notes: 5, 6, 7, 8, 9, 12, 35) (v dd = +3.3v 0.3v) ac characteristics - fast page mode option -6 parameter symbol min max units notes access time from column address t aa 35 ns 23 column-address hold time (referenced to ras#) t ar 43 ns 22 column-address setup time t asc 2 ns 21 row-address setup time t asr 5 ns 23 column address to we# delay time t awd 57 ns 21, 28 access time from cas# t cac 20 ns 14, 23 column-address hold time t cah 15 ns 23 cas# pulse width t cas 15 10,000 ns cas# hold time (cbr refresh) t chr 8 ns 4, 22 cas# to output in low-z t clz 5 ns 21, 30 cas# precharge time t cp 10 ns 15 access time from cas# precharge t cpa 40 ns 23 cas# to ras# precharge time t crp 10 ns 23 cas# hold time t csh 58 ns 22 cas# setup time (cbr refresh) t csr 7 ns 4, 21 cas# to we# delay time t cwd 42 ns 21, 28 write command to cas# lead time t cwl 15 ns data-in hold time t dh 15 ns 23, 27 data-in setup time t ds -2 ns 22, 27 output disable t od 3 15 ns output enable t oe 15 ns oe# hold time from we# during read-modify-write cycle t oeh 13 ns 22, 26 output buffer turn-off delay t off 5 20 ns 19, 25, 33 oe# setup prior to ras# during hidden refresh cycle t ord 0 ns fast-page-mode read or write cycle time t pc 35 ns capacitance parameter symbol 16mb 32mb units notes input capacitance: a0-a11, b0, pde#, oe0#, oe2# c i 1 99pf2 input capacitance: we0#, we2#, cas0#, cas4# c i 2 99pf2 input capacitance: ras0#, ras2# c i 3 39 67 p f 2 input/output capacitance: dq0-dq71 c io 10 10 p f 2 output capacitance: pd1-pd8 c o 10 10 p f 2 max
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 10 2, 4 meg x 72 buffered dram dimms obsolete fast page mode ac electrical characteristics (notes: 5, 6, 7, 8, 9, 12, 35) (v dd = +3.3v 0.3v) ac characteristics - fast page mode option -6 parameter symbol min max units notes pde# to valid presence-detect data t pd 10 ns 32 pde# inactive to presence-detects inactive t pdoff 2 ns 31 fast-page-mode read-write cycle time t prwc 87 ns 21 access time from ras# t rac 60 ns 13 ras# to column-address delay time t rad 13 ns 17, 24 row-address hold time t rah 8 ns 22 ras# pulse width t ras 60 10,000 ns ras# pulse width (fast page mode) t rasp 60 125,000 ns random read or write cycle time t rc 110 ns ras# to cas# delay time t rcd 18 ns 16, 24 read command hold time (referenced to cas#) t rch 2 ns 18, 21 read command setup time t rcs 2 ns 21 refresh period (2,048 cycles) (16mb) t ref 32 ms refresh period (4,096 cycles) (32mb) t ref 64 ms ras# precharge time t rp 40 ns ras# to cas# precharge time t rpc 0 ns read command hold time (referenced to ras#) t rrh 0 ns 18 ras# hold time t rsh 20 ns 23 read-write cycle time t rwc 160 ns 23 ras# to we# delay time t rwd 87 ns 21, 28 write command to ras# lead time t rwl 20 ns 23 transition time (rise or fall) t t250ns write command hold time t wch 15 ns 23 write command hold time (referenced to ras#) t wcr 43 ns 22 we# command setup time t wcs 2 ns 21, 28 write command pulse width t wp 10 ns we# hold time (cbr refresh) t wrh 8 ns 22 we# setup time (cbr refresh) t wrp 12 ns 21
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 11 2, 4 meg x 72 buffered dram dimms obsolete edo page mode ac electrical characteristics (notes: 5, 6, 7, 8, 9, 12, 35) (v dd = +3.3v 0.3v) ac characteristics - edo page mode option -5 -6 parameter symbol min max min max units notes access time from column address t aa 30 35 ns 23 column-address setup to cas# precharge t ach 12 15 ns column-address hold time (referenced to ras#) t ar 36 43 ns 22 column-address setup time t asc 2 2 ns 21 row-address setup time t asr 5 5 ns 23 column address to we# delay time t awd 44 51 ns 21, 28 access time from cas# t cac 18 20 ns 14, 23 column-address hold time t cah 13 15 ns 23 cas# pulse width t cas 8 10,000 10 10,000 ns cas# hold time (cbr refresh) t chr 6 8 ns 4, 22 cas# to output in low-z t clz 2 2 ns 21 data output hold after next cas# low t coh 5 5 ns 21 cas# precharge time t cp 8 10 ns 15 access time from cas# precharge t cpa 33 40 ns 23 cas# to ras# precharge time t crp 10 10 ns 23 cas# hold time t csh 36 43 ns 22 cas# setup time (cbr refresh) t csr 7 7 ns 4, 21 cas# to we# delay time t cwd 30 37 ns 21, 28 write command to cas# lead time t cwl 8 10 ns data-in hold time t dh 13 15 ns 23, 27 data-in setup time t ds -2 -2 ns 22, 27 output disable t od 0 12 0 15 ns output enable t oe 12 15 ns oe# hold time from we# during t oeh 6 8 ns 22, 26 read-modify-write cycle oe# high hold from cas# high t oehc 5 10 ns 26 oe# high pulse width t oep 5 5 ns oe# low to cas# high setup time t oes 4 5 ns output buffer turn-off delay t off 2 17 2 20 ns 19, 25, 33
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 12 2, 4 meg x 72 buffered dram dimms obsolete edo page mode ac electrical characteristics (notes: 5, 6, 7, 8, 9, 12, 35) (v dd = +3.3v 0.3v) ac characteristics - edo page mode option -5 -6 parameter symbol min max min max units notes oe# setup prior to ras# t ord 0 0 ns during hidden refresh cycle edo-page-mode read or write cycle time t pc 20 25 ns pde# to valid presence-detect data t pd 10 10 ns 32 pde# inactive to presence-detect inactive t pdoff 2 2 ns 31 edo-page-mode read-write cycle time t prwc 49 58 ns 21 access time from ras# t rac 50 60 ns 13 ras# to column-address delay time t rad 7 10 ns 17, 22 row-address hold time t rah 7 8 ns 22 ras# pulse width t ras 50 10,000 60 10,000 ns ras# pulse width (edo page mode) t rasp 50 125,000 60 125,000 ns random read or write cycle time t rc 84 104 ns ras# to cas# delay time t rcd 9 12 ns 16, 24 read command hold time (referenced to cas#) t rch 2 2 ns 18, 21 read command setup time t rcs 2 2 ns 21 refresh period (2,048 cycles) (16mb) t ref 32 32 ms refresh period (4,096 cycles) (32mb) t ref 64 64 ms ras# precharge time t rp 30 40 ns ras# to cas# precharge time t rpc 5 5 ns read command hold time (referenced to ras#) t rrh 0 0 ns 18 ras# hold time t rsh 18 20 ns 23 read-zwrite cycle time t rwc 121 145 ns 23 ras# to we# delay time t rwd 69 81 ns 21, 28 write command to ras# lead time t rwl 18 20 ns 23 transition time (rise or fall) t t250250ns write command hold time t wch 13 15 ns 23 write command hold time (referenced to ras#) t wcr 36 43 ns 22 we# command setup time t wcs 2 2 ns 21, 28 output disable delay from we# t whz 2 17 2 20 ns 25 write command pulse width t wp 5 5 ns we# pulse to disable at cas# high t wpz 10 10 ns we# hold time (cbr refresh) t wrh 6 8 ns 22 we# setup time (cbr refresh) t wrp 10 12 ns 21
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 13 2, 4 meg x 72 buffered dram dimms obsolete notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd = +3.3v; f = 1 mhz. 3. i cc is dependent on output loading. specified values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. an initial pause of 100s is required after power- up, followed by eight ras# refresh cycles (ras#-only or cbr with we# high), before proper device operation is ensured. the eight ras# cycle wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 5ns for fpm and 2.5ns for edo. 8. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il (or between v il and v ih ). 9. in addition to meeting the transition rate specification, all input signals must transit between v ih and v il (or between v il and v ih ) in a mono- tonic manner. 10.if cas# = v ih , data output is high-z. 11.if cas# = v il , data output may contain data from the last valid read cycle. 12.measured with a load equivalent to two ttl gates and 100pf and v ol = 0.8v and v oh = 2v. 13.requires that t aa and t cac are not violated. 14.requires that t aa and t rac are not violated. 15.if cas# is low at the falling edge of ras#, q will be maintained from the previous cycle. to initiate a new cycle and clear the data-out buffer, cas# must be pulsed high for t cp. 16.the t rcd (max) limit is no longer specified. t rcd (max) was specified as a reference point only. if t rcd was greater than the specified t rcd (max) limit, then access time was controlled exclusively by t cac ( t rac [min] no longer applied). with or without the t rcd (max) limit, t aa and t cac must always be met. 17.the t rad (max) limit is no longer specified. t rad (max) was specified as a reference point only. if t rad was greater than the specified t rad (max) limit, then access time was controlled exclusively by t aa ( t rac and t cac no longer applied). with or without the t rad (max) limit, t aa, t rac and t cac must always be met. 18.either t rch or t rrh must be satisfied for a read cycle. 19. t off (max) defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . 20.a hidden refresh may also be performed after a write cycle. in this case, we# = low and oe# = high. 21.a +2ns timing skew from the dram to the module resulted from the addition of line drivers. 22.a -2ns timing skew from the dram to the module resulted from the addition of line drivers. 23.a +5ns timing skew from the dram to the module resulted from the addition of line drivers. 24.a -2ns (min) and a -5ns (max) timing skew from the dram to the module resulted from the addition of line drivers. 25.a +2ns (min) and a +5ns (max) timing skew from the dram to the module resulted from the addition of line drivers. 26.late write and read-modify-write cycles must have both t od and t oeh met (oe# high during write cycle) in order to ensure that the output buffers will be open during the write cycle. the dqs will provide the previously read data if cas# remains low and oe# is taken back low after t oeh is met. if cas# goes high prior to oe# going back low, the dqs will remain open. 27.these parameters are referenced to cas# leading edge in early write cycles and we# leading edge in late write or read-modify-write cycles. 28. t wcs, t rwd, t awd and t cwd are not restrictive operating parameters. t wcs applies to early write cycles. t rwd, t awd and t cwd apply to read-modify-write cycles. if t wcs 3 t wcs (min), the cycle is an early write cycle and the data output will remain an open circuit through- out the entire cycle. if t wcs < t wcs (min) and t rwd 3 t rwd (min), t awd 3 t awd (min) and t cwd 3 t cwd (min), the cycle is a read- modify-write and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of data-out is indeterminate. oe# held high and we# taken low after cas# goes low result in a late write (oe#-controlled) cycle. t wcs, t rwd, t cwd and t awd are not applicable in a late write cycle. 29.column address changed once each cycle. 30.the 3ns minimum parameter guaranteed by design.
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 14 2, 4 meg x 72 buffered dram dimms obsolete notes (continued) 31. t pdoff max is determined by the pull-up resistor value. care must be taken to ensure adequate recovery time prior to reading valid up-level on subsequent dimm position. 32.measured with specified current load and 100pf. 33.with the fpm option, t off is determined by the first ras# or cas# signal to transition high. in comparison, t off on an edo option is deter- mined by the latter of the ras# and cas# signals to transition high. 34.applies to both fpm and edo operating modes. 35.if oe# is tied permanently low, late write or read-modify-write operations are not possible. 36. v ih overshoot: v ih (max) = v dd + 2v for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate.
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 15 2, 4 meg x 72 buffered dram dimms obsolete read cycle 34 note: 1. for edo, t off is referenced from rising edge of ras# or cas#, whichever occurs last. for fpm, t off is referenced from rising edge of ras# or cas#, whichever occurs first. t rrh t clz t cac t rac t aa valid data open t off t rch row t rcs t asc t rah t rad t ar t cah t rcd t cas t rsh t csh t rp t rc t ras t crp t asr row open ras# v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il t od t oe oe# v v ih il column cas# we# note 1 dont care undefined -5* -6 symbol min max min max units t off (edo) 2 17 2 20 ns t off (fpm) C C 5 20 ns t r a c 50 60 n s t rad (edo) 7 10 ns t rad (fpm) C 13 ns t rah 7 8 ns t ras 50 10,000 60 10,000 ns t rc (edo) 84 104 ns t rc (fpm) C 110 ns t rcd (edo) 9 12 ns t rcd (fpm) C 18 ns t rch 2 2 ns t rcs 2 2 ns t rp 30 40 n s t rrh 0 0 ns t rsh1820ns fast page mode and edo page mode timing parameters -5* -6 symbol min max min max units t a a 30 35 n s t ach (edo) 12 15 ns t ar 36 43 n s t asc 2 2 ns t asr 5 5 ns t c a c 18 20 n s t c a h 13 15 n s t cas (edo) 8 10,000 10 10,000 ns t cas (fpm) C C 15 10,000 ns t clz (edo) 2 2 ns t clz (fpm) C 5 ns t crp 10 10 n s t csh (edo) 36 43 ns t csh (fpm) C 58 ns t od (edo) 0 12 0 15 ns t od (fpm) C C 3 15 ns t oe 12 15 n s *edo version only
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 16 2, 4 meg x 72 buffered dram dimms obsolete early write cycle 34 dont care undefined v v ih il valid data row column row t ds t wp t wch t wcs t wcr t rwl t cwl t cah t asc t rah t asr t rad t ar t cas t rsh t csh t rcd t crp t ras t rc t rp v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# t dh we# cas# t ach *edo version only -5* -6 symbol min max min max units t rad (edo) 7 10 ns t rah 7 8 ns t ras 50 10,000 60 10,000 ns t rc (fpm) C 110 ns t rc (edo) 84 104 ns t rcd (fpm) C 18 ns t rcd (edo) 9 12 ns t rp 30 40 n s t rsh1820ns t rwl 18 20 n s t wch1315ns t w c r 36 43 n s t wcs 2 2 ns t wp (fpm) C 10 ns t wp (edo) 5 5 ns fast page mode and edo page mode timing parameters -5* -6 symbol min max min max units t ach (edo) 12 15 ns t ar 36 43 n s t asc 2 2 ns t asr 5 5 ns t c a h 13 15 n s t cas (fpm) C C 15 10,000 ns t cas (edo) 8 10,000 10 10,000 ns t crp 10 10 n s t csh (fpm) C 58 ns t csh (edo) 36 43 ns t cwl (fpm) C 15 ns t cwl (edo) 8 10 ns t d h 13 15 n s t ds -2 -2 ns t rad (fpm) C 13 ns
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 17 2, 4 meg x 72 buffered dram dimms obsolete fast-page-mode read cycle t rrh t clz t cac t rac t aa valid data open t off t rch row t rcs t asc t rah t rad t ar t cah t ral t rcd t cas t rsh t csh t rp t rc t ras t crp t asr row open ras v v ih il cas v v ih il addr v v ih il dq v v ioh iol v v ih il t od t oe oe v v ih il column we dont care undefined -6 symbol min max units t oe 15 ns t off 5 20 ns t pc 35 ns t rac 60 ns t rad 13 ns t rah 8 ns t rasp 60 125,000 ns t rcd 18 ns t rch 2 ns t rcs 2 ns t rp 40 ns t rrh 0 ns t rsh 20 ns fast page mode timing parameters -6 symbol min max units t aa 35 ns t ar 43 ns t asc 2 ns t asr 5 ns t cac 20 ns t cah 15 ns t cas 15 10,000 ns t clz 5 ns t cp 10 ns t cpa 40 ns t crp 10 ns t csh 58 ns t od 3 15 ns
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 18 2, 4 meg x 72 buffered dram dimms obsolete edo-page-mode read cycle valid data valid data valid data column column column row row dont care undefined t od t cah t asc t cp t rsh t cp t cp t cas t rcd t crp t pc t csh t rasp t rp t cah t asc t cah t asc t ar t rah t rad t asr t rcs t rrh t rch t off t cac t cpa t aa t clz t cac t cpa t aa t cac t rac t aa t clz t oe t od t oe t od open open v v ih il v v ih il addr v v ih il v v ih il dq v v oh ol v v ih il ras# oe# t cas t cas cas# we# t coh t oep t oehc t oes t oes t ach t ach t ach -5 -6 symbol min max min max units t oehc 5 10 ns t oep 5 5 ns t oes 4 5 ns t off 2 17 2 20 ns t pc 20 25 n s t r a c 50 60 n s t rad 7 10 ns t rah 7 8 ns t rasp 50 125,000 60 125,000 ns t rcd 9 12 ns t rch 2 2 ns t rcs 2 2 ns t rp 30 40 n s t rrh 0 0 ns t rsh1820ns edo page mode timing parameters -5 -6 symbol min max min max units t a a 30 35 n s t a c h 12 15 n s t ar 36 43 n s t asc 2 2 ns t asr 5 5 ns t c a c 18 20 n s t c a h 13 15 n s t cas 8 10,000 10 10,000 ns t clz 2 2 ns t coh 5 5 ns t cp 8 10 ns t cpa 33 40 n s t crp 10 10 n s t c s h 36 43 n s t od 0 12 0 15 ns t oe 12 15 n s
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 19 2, 4 meg x 72 buffered dram dimms obsolete fast/edo-page-mode early write cycle 34 *edo version only t ds t dh t ds t dh t ds t dh t wcr valid data valid data valid data t rwl t wp t cwl t wch t wcs t wp t cwl t wch t wcs t wp t cwl t wch t wcs t cah t asc t cah t asc t cah t asc t rah t asr t rad t ach t ach t ach t ar column column column row row t cp t cas t rsh t cp t cas t cp t cas t rcd t crp t pc t csh t rasp t rp v v ih il cas# v v ih il addr v v ih il we# v v ih il dq v v ioh iol ras# dont care undefined -5* -6 symbol min max min max units t pc (fpm) C 35 ns t rad (edo) 7 10 ns t rad (fpm) C 13 ns t rah 7 8 ns t rasp 50 125,000 60 125,000 ns t rcd (edo) 9 12 ns t rcd (fpm) C 18 ns t rp 30 40 n s t rsh1820ns t rwl 18 20 n s t wch1315ns t w c r 36 43 n s t wcs 2 2 ns t wp (edo) 5 5 ns t wp (fpm) C 10 ns fast page mode and edo page mode timing parameters -5* -6 symbol min max min max units t ach (edo) 12 15 ns t ar 36 43 n s t asc 2 2 ns t asr 5 5 ns t c a h 13 15 n s t cas (edo) 8 10,000 10 10,000 ns t cas (fpm) C C 15 10,000 ns t cp 8 10 ns t crp 10 10 n s t csh (edo) 36 43 ns t csh (fpm) C 58 ns t cwl (edo) 8 10 ns t cwl (fpm) C 15 ns t d h 13 15 n s t ds -2 -2 ns t pc (edo) 20 25 ns
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 20 2, 4 meg x 72 buffered dram dimms obsolete read-write cycle 34 (late write and read-modify-write cycles) valid d out valid d in row column row v v ih il v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# open open t oe t od t cac t rac t aa t clz t ds t dh t awd t wp t rwl t cwl t cwd t rwd t rcs t asc t cah t ar t asr t rad t crp t rcd t cas t rsh t csh t ras t rwc t rp t rah oe# t oeh we# t ach cas# dont care undefined *edo version only -5* -6 symbol min max min max units t od (edo) 0 12 0 15 ns t od (fpm) C C 3 15 ns t oe 12 15 n s t oeh (edo) 6 8 ns t oeh (fpm) C 13 ns t r a c 50 60 n s t rad (edo) 7 10 ns t rad (fpm) C 13 ns t rah 7 8 ns t ras 50 10,000 60 10,000 ns t rcd (edo) 9 12 ns t rcd (fpm) C 18 ns t rcs 2 2 ns t rp 30 40 n s t rsh1820ns t rwc (edo) 121 145 ns t rwc (fpm) C 160 ns t rwd (edo) 69 81 ns t rwd (fpm) C 87 ns t rwl 18 20 n s t wp (edo) 5 5 ns t wp (fpm) C 10 ns fast page mode and edo page mode timing parameters -5* -6 symbol min max min max units t a a 30 35 n s t ach (edo) 12 15 ns t ar 36 43 n s t asc 2 2 ns t asr 5 5 ns t awd (edo) 42 49 ns t awd (fpm) C 57 ns t c a c 18 20 n s t c a h 13 15 n s t cas (edo) 8 10,000 10 10,000 ns t cas (fpm) C C 15 10,000 ns t clz (edo) 2 2 ns t clz (fpm) C 5 ns t crp 10 10 n s t csh (edo) 36 43 ns t csh (fpm) C 58 ns t cwd (edo) 30 37 ns t cwd (fpm) C 42 ns t cwl (edo) 8 10 ns t cwl (fpm) C 15 ns t d h 13 15 n s t ds -2 -2 ns
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 21 2, 4 meg x 72 buffered dram dimms obsolete fast/edo-page-mode read-write cycle 34 (late write and read-modify-write cycles) dont care undefined t oe t oe t oe open d out valid d in valid d out valid d in valid d out valid d in valid open t dh t ds t aa t cpa t clz t cac t dh t ds t aa t cpa t clz t cac t dh t ds t aa t clz t cac t rac t wp t cwl t rwl t cwd t awd t wp t cwl t cwd t awd t wp t cwl t cwd t awd t rcs t rwd t asr t rah t asc t rad t ar t cah t asc t cah t asc t cah t cp t cas t rsh t cp t rp t rasp t cas t cp t cas t rcd t csh t pc t crp row column column column row v v ih il cas# v v ih il addr v v ih il v v ih il dq v v ioh iol v v ih il ras# oe# we# t prwc t oeh t od t od t od note 1 note: 1. t pc is for late write cycles only. *edo version only -5* -6 symbol min max min max units fast page mode and edo page mode timing parameters -5* -6 symbol min max min max units t a a 30 35 n s t ar 36 43 n s t asc 2 2 ns t asr 5 5 ns t awd (edo) 42 49 n s t awd (fpm) C 57 n s t c a c 18 20 n s t c a h 13 15 n s t cas (edo) 8 10,000 10 10,000 ns t cas (fpm) CC 15 10,000 ns t clz (edo) 22ns t clz (fpm) C 5ns t cp 8 10 ns t cpa 33 40 n s t crp 10 10 n s t csh (edo) 36 43 n s t csh (fpm) C 58 n s t cwd (edo) 30 37 n s t cwd (fpm) C 42 n s t cwl (edo) 810ns t cwl (fpm) C 15 n s t d h 13 15 n s t ds -2 -2 ns t od (edo) 012015ns t od (fpm) CC 315ns t oe 12 15 n s t oeh (edo) 68ns t oeh (fpm) C 13 n s t pc (edo) 20 25 n s t pc (fpm) C 35 n s t prwc (edo) 49 58 n s t prwc (fpm) C 87 n s t r a c 50 60 n s t rad (edo) 710ns t rad (fpm) C 13 n s t rah 7 8 ns t rasp 50 125,000 60 125,000 ns t rcd (edo) 912ns t rcd (fpm) C 18 n s t rcs 2 2 ns t rp 30 40 n s t rsh1820ns t rwd (edo) 69 81 n s t rwd (fpm) C 87 n s t rwl 18 20 n s t wp (edo) 55ns t wp (fpm) C 10 n s
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 22 2, 4 meg x 72 buffered dram dimms obsolete edo-page-mode read early write cycle (pseudo read-modify-write) v v ih il v v ih il ras# v v ih il addr v v ih il we# t rasp t rp row column (a) column (n) row v v ih il oe# v v ioh iol t crp t csh t cas t rcd t asr t rah t rad t asc t ar t cah t asc t cah t asc t cah t cp t rsh valid data in t rcs t rch t wcs t oe valid data (b) valid data (a) t whz t cac t cpa t aa t cac t aa open dq t pc rac t t coh t wch t ds t dh t pc column (b) t ach cas# t cas t cas t cp t cp dont care undefined -5 -6 symbol min max min max units t oe 12 15 n s t pc 20 25 n s t r a c 50 60 n s t rad 7 10 ns t rah 7 8 ns t rasp 50 125,000 60 125,000 ns t rcd 9 12 ns t rch 2 2 ns t rcs 2 2 ns t rp 30 40 n s t rsh1820ns t wch1315ns t wcs 2 2 ns t whz 2 17 2 20 ns edo page mode timing parameters -5 -6 symbol min max min max units t a a 30 35 n s t a c h 12 15 n s t ar 36 43 n s t asc 2 2 ns t asr 5 5 ns t c a c 18 20 n s t c a h 13 15 n s t cas 8 10,000 10 10,000 ns t coh 5 5 ns t cp 8 10 ns t cpa 33 40 n s t crp 10 10 n s t c s h 36 43 n s t d h 13 15 n s t ds -2 -2 ns
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 23 2, 4 meg x 72 buffered dram dimms obsolete fast-page-mode read early write cycle (pseudo read-modify-write) row valid data valid data open t crp t rcd t cas t rsh t rasp t rp t pc t asc t cah t ar t asr t rad t rah t wcs t wp t rwl t rcs t dh t ds t cac t off v v ih il cas# v v ih il addr v v ih il ras# dq v v oh ol we# v v ih il t csh column t cp t cp t asc t cah t cwl t wch t clz t aa rac dont care undefined t note 1 row column t cas note: 1. do not drive data prior to tristate. -6 symbol min max units t off 5 20 ns t pc 35 ns t rac 60 ns t rad 13 ns t rah 8 ns t rasp 60 125,000 ns t rcd 18 ns t rcs 2 ns t rp 40 ns t rsh 20 ns t rwl 20 ns t wch 15 ns t wcs 2 ns t wp 10 ns fast page mode timing parameters -6 symbol min max units t aa 35 ns t ar 43 ns t asc 2 ns t asr 5 ns t cac 20 ns t cah 15 ns t cas 15 10,000 ns t clz 5 ns t cp 10 ns t crp 10 ns t csh 58 ns t cwl 15 ns t dh 15 ns t ds -2 ns
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 24 2, 4 meg x 72 buffered dram dimms obsolete edo read cycle (with we#-controlled disable) t clz t cac t rac t aa valid data open t rch t rcs t asc t rah t rad t ar t cah t rcd t cas t csh t crp t asr row open ras# v v ih il v v ih il addr v v ih il dq v v oh ol v v ih il t od t oe oe# v v ih il column we# t whz t wpz t cp t asc t rcs column t clz dont care undefined cas# -5 -6 symbol min max min max units t od 0 12 0 15 ns t oe 12 15 n s t r a c 50 60 n s t rad 7 10 ns t rah 7 8 ns t rcd 9 12 ns t rch 2 2 ns t rcs 2 2 ns t whz 2 17 2 20 ns t wpz 10 10 n s edo page mode timing parameters -5 -6 symbol min max min max units t a a 30 35 n s t ar 36 43 n s t asc 2 2 ns t asr 5 5 ns t c a c 18 20 n s t c a h 13 15 n s t cas 8 10,000 10 10,000 ns t clz 2 2 ns t cp 8 10 ns t crp 10 10 n s t c s h 36 43 n s
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 25 2, 4 meg x 72 buffered dram dimms obsolete ras#-only refresh cycle 34 row v v ih il cas# v v ih il addr v v ih il ras# t rc t ras t rp t crp t asr t rah row open dq v v oh ol t rpc we# v v ih il dont care undefined -5* -6 symbol min max min max units t rc (fpm) C 110 ns t rc (edo) 84 104 ns t rp 30 40 n s t rpc (fpm) C 0 ns t rpc (edo) 5 5 ns fast page mode and edo page mode timing parameters -5* -6 symbol min max min max units t asr 5 5 ns t crp 10 10 n s t csr 7 7 ns t rah 7 8 ns t ras 50 10,000 60 10,000 ns *edo version only
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 26 2, 4 meg x 72 buffered dram dimms obsolete cbr refresh cycle 34 (addresses, oe# = dont care) presence-detect read cycle 34 t pdoff pde# v v ih il pd1-pd8 v v ih il valid presence-detect t pd dont care undefined t rp v v ih il ras# t ras note 1 open t chr t csr v v ih il v v oh ol cas# dq t rp t ras t rpc t csr t rpc t chr t cp v v ih il t wrp t wrh we# t wrp t wrh note: 1. pd pins must be pulled high at next level of assembly. t rp 30 40 n s t rpc (fpm) C 0 ns t rpc (edo) 5 5 ns t wrh 6 8 ns t wrp 10 12 n s -5* -6 symbol min max min max units fast page mode and edo page mode timing parameters -5* -6 symbol min max min max units t chr 6 8 ns t cp 8 10 ns t csr 7 7 ns t pd 10 10 n s t pdoff 2 2 ns t ras 50 10,000 60 10,000 ns *edo version only
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 27 2, 4 meg x 72 buffered dram dimms obsolete hidden refresh cycle 20, 34 (we# = high; oe# = low) dont care undefined t clz t off open valid data open column row t cac t rac t aa t cah t asc t rah t asr t rad t ar t crp t rcd t rsh t ras t rc t rp t chr t ras dq v v ioh iol v v ih il addr v v ih il cas# v v ih il ras# t off (fpm) C C 5 20 ns t off (edo) 2 17 2 20 ns t ord 0 0 ns t r a c 50 60 n s t rad (fpm) C 13 ns t rad (edo) 7 10 ns t rah 7 8 ns t ras 50 10,000 60 10,000 ns t rcd (fpm) C 18 ns t rcd (edo) 9 12 ns t rp 30 40 n s t rsh1820ns -5* -6 symbol min max min max units fast page mode and edo page mode timing parameters -5* -6 symbol min max min max units t a a 30 35 n s t ar 36 43 n s t asc 2 2 ns t asr 5 5 ns t c a c 18 20 n s t c a h 13 15 n s t chr 6 8 ns t clz (fpm) C 5 ns t clz (edo) 2 2 ns t crp 10 10 n s t od (fpm) C C 3 15 ns t od (edo) 0 12 0 15 ns t oe 12 15 n s *edo version only
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 28 2, 4 meg x 72 buffered dram dimms obsolete .350 (8.89) max .054 (1.37) .046 (1.17) 1.005 (25.53) .995 (25.27) pin 1 5.256 (133.50) 5.244 (133.20) .700 (17.78) typ .118 (3.00) (2x) .118 (3.00) typ .250 (6.35) typ 4.550 (115.57) .050 (1.27) typ .118 (3.00) typ .039 (1.00) typ 2.625 (66.68) 1.700 (43.18) .079 (2.00) r (2x) .039 (1.00) r(2x) pin 84 front view back view pin 168 pin 85 .128 (3.25) .118 (3.00) (2x) 168-pin dimm df-7 (32mb) 168-pin dimm df-8 (16mb) .200 (5.08) max .054 (1.37) .046 (1.17) pin 1 (pin 85 on backside) .700 (17.78) typ .118 (3.00) (2x) .118 (3.00) typ .250 (6.35) typ 4.550 (115.57) .050 (1.27) typ .118 (3.00) typ .039 (1.00) typ .079 (2.00) r (2x) .039 (1.00) r(2x) front view .128 (3.25) .118 (3.00) pin 84 (pin 168 on backside) (2x) 1.700 (43.18) 2.625 (66.68) 1.005 (25.53) .995 (25.27) 5.256 (133.50) 5.244 (133.20) note: all dimensions in inches (millimeters) max or typical where noted. min
2, 4 meg x 72 buffered dram dimms micron technology, inc., reserves the right to change products or specifications without notice. dm33.p65 C rev. 2/99 ?1999, micron technology, inc. 29 2, 4 meg x 72 buffered dram dimms obsolete 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micronsemi.com, internet: http://www.micronsemi.com, customer comment line: 800-932-4992 micron is a registered trademark of micron technology, inc.

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